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TC94A58FAG 2005-12-7 1 toshiba cmos digital integrated circuit silicon monolithic TC94A58FAG single-chip cd processor with built-in controller the TC94A58FAG is a single-chip cd processor for digital servo, which incorporates a 4-bit microcontroller. the controller features an lcd driver, 4-channel 6-bit ad converter, 1 port 2-channel 2/3-line or uart serial interface module, a buzzer, 20-bit general-purpose counter function, interrupt function, and 8-bit timer/counter. the cpu can select one of four operating clocks (16.9344-mhz, 75-khz or 32.768-khz crystal oscillator and external clock input), facilitating interface with the cd processor. the cd processor incorporates sync separation protection and interpolation, efm demodulator, error correction, digital equalizer for servo, and servo controller. the cd processor also incorporates a 1-bit da converter. in combination with the ta2157f/fg/fn/fng digital servo head amplifier, the TC94A58FAG can very simply configure an adjustment-free cd player. thus, the ic is suitable for cd systems for automobiles and radio-cassette players. features ? single-chip cd processor with on-chip cmos lcd driver and 4-bit microcontroller ? operating supply voltage: cd in operation: v dd = 3.0 to 3.6 v (3.3 v typ.) cd stopped: v dd = 1.8 to 3.6 v (only cpu in operation) ? supply current: cd in operation: i dd = 30 ma (typ.) cd stopped: i dd = 1.5 ma (cd standby mode, with 16.9344-mhz crystal oscillator, cpu in operation) cd stopped: i dd = 50 a (cd standby mode, with 75-khz crystal oscillator, cpu in operation) ? operating temperature range: ta = ? 40 to 85c ? package: lqfp (0.5-mm pitch, 1.4 mm thick) ? e 2 prom: tc94ae29fag weight: 0.32 g (typ.)
TC94A58FAG 2005-12-7 2 4-bit microcontroller ? program memory (rom): 16 bits 16 ksteps ? data memory (ram): 4 bits 512 words ? instruction execution time: 1.42 s, 40 s, 91.6 s, tosc 3 (every instruction consists of a single word.) ? crystal oscillator frequency: 16.9344 mhz, 75 khz, 32.768 khz, external clock input ? stack levels: 16 ? ad converter: 6 bits 4 channels ? lcd driver: 1/4 duty, 1/2 or 1/3 bias method, 64 segments (max) ? i/o ports: cmos i/o ports: 26 (max) n-channel open-drain i/o ports (for up to 5.5 v): 3 (max) ? timer/counter: 8 bits (timer mode, pulse width detector and measure function) ? general-purpose counter: 20 bits, 0.1 mhz to 20 mhz, vin = 0.2 vpp (min), input amplifier incorporated ? serial interface module: 1 port 2 channel supporting 2/3-line method or uart (two input channels) ? four buzzer types: 0.75 khz, 1 khz, 1.5 khz, and 3 khz ? four modes: continuous, single-shot, 10 hz intermittent, and 10 hz intermittent at 1 hz intervals ? interrupts: 1 external, 3 internal (cd sub-sync, serial interface, 8-bit timer) ? back-up mode: four types: cd standby (cd processor stopped) clock stop (oscillator stopped) hardware wait (only crystal oscillator in operation) software wait (cpu in intermittent operation) ? reset function: power-on reset circuit, supply voltage detector (detection voltage = 1.5 v typ.) ? multiplexed cd processor pins: each of the following pins can be switched by program to a cd processor-dedicated pin: dsp output: bck, lrck, aout, dout, ipf, sbok, clck, data, and sfsy pins. dac input: dacin, bckin, and lrckin pins. note: bckin and lrckin are switched as a pair. a cd command is used to specify dac input settings. cd processor ? reliable sync pattern detection, sync signal protection and interpolation ? built-in efm demodulator and subcode decoder ? high-correction capability using cross interleave read solomon code (circ) logical equation c1 correction: dual c2 correction: quadruple ? jitter absorption capability of 6 frames ? built-in 16 kb ram ? built-in digital output circuit ? built-in l/r independent digital attenuator ? bilingual audio output ? audio output: 32fs, 48fs or 64fs selectable ? subcode q data is read-timing free and can be driven out in sync with audio data. ? built-in data slicer and analog pll (adjustment-free vco used) circuit ? automatic adjustment of loop gain, offset, and balance at focus servo and tracking servo ? built-in rf gain auto-adjusting circuit ? built-in digital equalizer for phase compensation ? supports different pickups using on-chip digital equalizer coefficient ram. ? built-in focus and tracking servo control circuit ? search control supports all modes and realizes high-speed, stable search. ? lens kick and feed kick use speed control method. ? built-in afc and apc circuits for disc motor clv servo ? built-in defect/shock detector ? built-in 8 times over-sampling digital filter and 1-bit da converter ? built-in analog filter for 1-bit da converter
TC94A58FAG 2005-12-7 3 ? built-in zero-data detection output circuit ? supports double-speed operation. note: output pins for subcode q data and audio data have multiplexed functions for controller-dedicated pins. the function of each pin can be switched by program.
TC94A58FAG 2005-12-7 4 pin connections tezi lqfp -64 (0.5-mm pitch) top view dvr lo dv ss ro dv dd cv ss xi xo cv dd dmo fmo sel tebc rfgc tro foo 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 25 26 24 23 22 21 20 19 18 17 49 50 51 52 53 54 57 58 60 61 62 63 64 55 56 59 1 2 4 7 10 11 12 13 14 15 16 356 reset p8-0/mxi/sysck (brk1) p8-1/mxo/dacin (brk2) p2-0/com1 p2-1/com2 p2-2/com3 p2-3/com4 test/p3-0/s1 p3-1/s2 p3-2/s3 p3-3/s4 p4-0/s5 p4-1/s6 p4-2/s7 p4-3/s8 p5-0/s9 p5-1/s10/bck (brk3) p5-2/s11/lrck (brk4) p5-3/s12/aout (brk5) p6-0/s13/adin1/dout/bckin brk6) p6-1/s14/adin2/ipf/lrckin (brk7) p6-2/s15/adin3/sbok (brk8) p6-3/s16/adin4/clck (brk9) mv dd mv ss p1-0/sck1/rx1/ctin/data (brk10) p1-1/sdio1/tx1/sfsy (brk11) p1-2/si1/sbsy (brk12) p1-3/buzr (brk13) p7-0/sck2/rx2 (brk14) p7-1/sdio2/tx2 (brk15) p7-2/intr/si2 (brk16) tei sbad fei rfrp rfzi v ref av dd rfi slco av ss vcof lpfo lpfn tmax pdo 1-bit dac 16.9344-mhz oscillator cd processor-dedicated control input/output pins 75-khz/32.768-khz oscillator external clock input/ dac data in p ut lcd driver (4 16 = 64 segments max.) ad converter controller-dedicated pins serial interface 1 8 9 pull-up/pull-down can be specified. reset inpu t test mode input cmos i/o ports (up to 26 ports) pull-up/pull-down can be specified. also used for cd function n-ch open-drain i/o (3 pins, 5.5 v max.) serial interface 2 interrupt inpu t buzzer outpu t frequency counter inpu t note: for brk1 to brk16, the backup state can be set to be released in port units. note: the test pin (pin 56) is pulled down during a reset, thus accepting test mode input. therefore, it should be applied low or left open during a reset.
TC94A58FAG 2005-12-7 5 block diagram p7-0/sck2/rx2 (brk14) dv r lo ro dv ss dv dd tma x pdo vcof mv ss mv dd a v ss a v dd rfzi rfrp fei sbad tei tezi foo fmo dmo sel tro tebc rfgc v ref p7-2/intr/si2 (brk16) p7-1/sdio2/tx2 (brk15) xo xi cv dd cv ss lpfn rfi slco lpfo x?tal osc lpf mpx clock gene. cpu clock cr osc lcd driver/io port2, 3, 4, 5, 6 port1 bias 1 bit dac zdet pwm cd clock v ref sbsy da servo control digital equalizer automatic adjustment circuit rom ram 16 k sram clv servo v ref synchronous guarantee efm decode sub code decoder data slicer v ref pll tmax vco correction circuit address ad digital out audio out micon interface data reg (16 bit) mask rom (16 16384 step) program counter stack reg. (16level) g-reg. r/w buf. alu power on reset f/f reset bck, lrck, aout, dout, ipf, sbok, clck, data, sfsy, sbsy ram (4 512 word) instruction decoder sbsy bck, lrck, aout, dout ipf, sbok, clck, data, sfsy cd reset reset v ref v ref v ref x?tal osc port8 timer interrupt cont. serial interface (sio) port7 buzr 20 bit counter ad conv. p2-0/com1 sio reset p2-1/com2 p2-2/com3 p2-3/com4 test/p3-0/s1 p3-1/s2 p5-0/s9 p5-1/s10/bck (brk3) p5-2/s11/lrck (brk4) p5-3/s12/aout (brk5) p6-0/s13/adin1/dout/bckin (brk6) p6-1/s14/adin2/ipf/lrckin (brk7) p6-2/s15/adin3/sbok (brk8) p6-3/s16/adin4/clck (brk9) p1-0/sck1/rx1/ctin/data (brk10) p1-1/sdio1/tx1/sfsy (brk11 ) p1-2/si1/sbsy (brk12) p1-3/buzr (brk13) p8-1/mxo/dacin (brk2) intr bckin, lrckin dacin dacin,bckin, lrckin p8-0/mxi/sysck (brk1)
TC94A58FAG 2005-12-7 6 pin functions pin no. symbol pin name function and operation remarks 49 reset reset input system reset input pin for the device. a reset is applied while the reset signal is low. when it is high, the 16.9344-mhz crystal oscillator (xi, xo) starts operating. the controller counts clock pulses from this oscillator and waits a specified standby time (approximately 50 ms) before starting the controller program from address 0. the cd processor is placed in the standby state at this time. normally, raising the voltage on mvdd from 0 to 1.8 v or higher triggers a system reset (power-on reset) so that the reset pin should be held at high. 50 51 p8-0 /mxi/sysck (brk1) p8-1 /mxo /dacin (brk2) i/o port 8-0 /crystal oscillator /cpu clock input i/o port 8-1 /crystal oscillator /1-bit dac data input 2-bit cmos i/o port. input/output can be specified for each bit. when the pins are used as i/o port input, each pin can be pulled up or down by program. when backup release for clock stop mode or wait mode is enabled for the pins, a change in a pin can release the backup state. the program can set these pins to be used for a 75-khz or 32.768-khz dedicated crystal oscillator. the p8-0 pin can also be used to accept an external cpu operating clock input (sysck). the p8-1 pin can also be used to accept data for the 1-bit dac (dacin) when a cd command is executed. the 75-khz or 32.768-khz dedicated crystal oscillator and cpu clock input are used for the operation of the controller and peripheral devices. upon a system reset, the 16.9344-mhz crystal oscillator (xi, xo) is selected as the clock for controller and peripheral device operation. the program can subsequently set the pins to oscillator pins and switch the clock generated from the oscillator to the controller clock. when the pins are used for an oscillator, executing the ckstp instruction causes its oscillation to stop. (note) when the p8-0 pin is used for a cr oscillator, the p8-1 pin can used as an i/o port pin. (note) backup release is enabled for both pins simultaneously. (note) use a crystal oscillator having a good startup characteristic. (note) upon a system reset, the pins are set to i/o port input. (note) after setting the pins to oscillator pins, wait until oscillation settles before switching the controller clock. (note) for an external cpu clock, usually use a 32.768-khz clock. the pin has cmos input configuration. mv dd mv ss mxo r out2 r fxt2 mxi mv dd mv ss (when used for crystal oscillator) mv dd mv dd r in1 mv dd input instructio mv ss (when used for i/o port)
TC94A58FAG 2005-12-7 7 pin no. symbol pin name function and operation remarks 52 53 54 55 p2-0/com1 p2-1/com2 p2-2/com3 p2-3/com4 i/o port 2 /lcd common output 56 test /p3-0/s1 test input /i/o port 3-0 /lcd segment output 57 58 59 p3-1/s2 p3-2/s3 p3-3/s4 i/o port 3 /lcd segment output 60 61 62 63 p4-0/s5 p4-1/s6 p4-2/s7 p4-3/s8 i/o port 4 /lcd segment output 24-bit cmos i/o port and 3-bit n-channel open-drain i/o port. input/output can be specified for each bit. when the p6-0 to p6-3 pins are used as i/o port input, each pin can be pulled up or down by program. when the p5-1 (brk3) to p7-2 (brk16) pins are used as i/o port input and backup release for clock stop mode or wait mode is enabled for those pins (enabled/disabled in port units), a change in any of the pins can release the backup state. the p7-0 to p7-2 pins constitute an n-channel open-drain i/o port, to which a voltage of up to 5.5 v can be applied. i/o ports 2 to 6 can be set to lcd driver output pins by program. the com1 to com4 pins drive common signals to the lcd panel while the s1 to s16 pins drive segment signals. the com1 to com4 signals configure a matrix with the s1 to s16 signals to display up to 64 segments. when the lcdoff bit is set to 0, the com1 to com4 and s1 to s4 pins are collectively set to lcd output. for s5 to s16, the program can specify either i/o port or segment output individually for each pin. the lcd can be driven by the 1/4-duty, 1/2-bias method (frame frequency: 62.5 hz) or the 1/4-duty, 1/3-bias method (frame frequency: 125 hz). when the 1/2 bias method is set, three common output levels (mvdd, 1/2mvdd and gnd) and two segment output levels (mvdd and gnd) appear on the pins. when the 1/3 bias method is set, four common and segment output levels (mvdd, 1/3mvdd, 2/3mvdd and gnd) appear on the pins. after clock stop mode is released, a non-select waveform (bias voltage) is driven and the disp off bit is set to 0, after which the common signals are driven. during a system reset ( reset = low), the test/p3-0/s1 pin is pulled down and accepts test mode input. this pin should be left open or applied low level during a reset. the p5-1 to p6-3 and p1-0 to p1-2 pins can be set to cd processor-dedicated pins on a per pin basis. the cd processor functions are as follows: (continued on next page) mv dd mv dd input instruction lcd volta g e mv dd mv dd input instruction lcd volta g e r in2 mv ss reset signal mv dd mv dd input instruction lcd volta g e
TC94A58FAG 2005-12-7 8 pin no. symbol pin name function and operation remarks 64 p5-0/s9 i/o port 5-0 /lcd segment output 1 2 3 p5-1/s10 /bck (brk3) p5-2/s11 /lrck (brk4) p5-3/s12 /aout (brk5) i/o port 5 /lcd segment output /cd processor function 4 5 6 7 p6-0/s13 /adin1 /dout /bckin (brk6) p6-1/s14 /adin2 /ipf /lrckin (brk7) p6-2/s15 /adin3 /sbok (brk8) p6-3/s16 /adin4 /clck (brk9) i/o port 6 /lcd segment output /cd processor function bck: bit clock output pin. one of three frequencies, 32, 48 or 64 can be specified using a cd command. at normal speed: 32 f s = 1.4112 mhz lrck: lr channel clock output pin. for the l channel, this pin drives a low level. for the r channel, it drives a high level. the polarity can be inverted using a cd command. at normal speed: 44.1 khz aout: audio data output pin. either msb first or lsb first can be specified using a cd command. dout: digital data output pin. it drives data at up to double speed (complying with cp-1201). ipf: correction flag output pin. if the aout output is c2 error detection/correction, a high level appears to indicate an uncorrectable symbol. (also called c2po) sbok: crcc test result output pin for subcode q data. a high level appears when the data has passed the test. clck: clock input/output pin for reading subcode p to w data. the input/output polarity can be inverted using a cd command. data: subcode p to w data output pin. sfsy: frame sync signal output pin for playback. sbsy: block sync signal output pin for subcode. when a subcode sync is detected, a high level appears at s1. the controller enables cd interrupts. when an interrupt occurs on the falling edge of the sbsy signal, the program jumps to address 2. bckin: bit clock input pin for 1-bit dac. lrckin: lr channel clock input pin for 1-bit dac (note) interrupts should not be enabled when cd processor operation is undefined. (note) unlike other cd processor pins, lrckin and bckin are configured as a pair so their functions are always switched together. when these pins are used, they should be set as i/o port input. p6-0 to p6-3 pins have multiplexed functions for the on-chip 6-bit 4-channel ad converter analog input. the on-chip ad converter uses successive approximation. the conversion time is 242 s when the 16.9344-mhz crystal oscillator is used and 7 instruction cycles (280 s) when the 75-khz crystal oscillator is used. the program can specify necessary pins for ad analog input on a per bit basis. the internal power supply (mv dd ) is used as the reference voltage. when the p6-0 to p6-3 pins are used as i/o port input, each pin can be pulled up or down by program. (continued on next page) mv dd mv dd input instruction lcd volta g e mv dd mv dd i nput instruction release enable lcd volta g e mv dd mv dd i nput instruction release enable lcd volta g e r in1 mv ss mv dd ad input
TC94A58FAG 2005-12-7 9 pin no. symbol pin name function and operation remarks 10 p1-0/sck1 /rx1 /ctin /data (brk10) i/o port 1-0 /serial clock input/output 1 /serial receive data 1 /counter clock input /cd processor function 11 p1-1/sdio1 /tx1 /sfsy (brk11) i/o port 1-1 /serial data input/output 1 /serial transmit data 1 /cd processor function 12 p1-2/si1 /sbsy (brk12) i/o port 1-2 /serial data input 1 /cd processor function 13 p1-3/buzr (brk13) i/o port 1-3 /buzzer output 14 p7-0/sck2 /rx2 (brk14) i/o port 7-0 /serial clock input/output 2 /serial receive data 2 15 p7-1/sdio2 /tx2 (brk15) i/o port 7-1 /serial data input/output 2 /serial transmit data 2 16 p7-2/intr /si2 (brk16) i/o port 7-2 /interrupt input /serial data input 2 the p1-0 pin has multiplexed functions for general-purpose counter input. the input frequency is 0.1 mhz to 20 mhz. the counter incorporates an input amplifier and operates with capacitance-coupled small amplitudes. the counter is a 20-bit counter and can store 20-bit data directly in memory. the gate time can be selected from among 1 ms, 4 ms, 16 ms and 64 ms (when the 75-khz crystal oscillator is used). in manual mode, the gate can be turned on and off within the specified time using instructions. the p1-0 to p1-2 and p7-0 to p7-2 pins have multiplexed functions for serial interface (sio) circuit input/output pins. the sio is a serial interface supporting 2-line and 3-line methods as well as uart. the TC94A58FAG has cmos input/output pins (sck1/rx1, sdio1/tx1, si1) and n-channel open-drain (supporting up to 5.5 v) input/output pins (sck2/rx2, sdio2/tx2, si2). one of the two sets of pins can be selected as serial interface. the serial interface circuit supports various options, including the number of the clock edge to be used, the serial clock input/output, and the clock frequency. these options facilitate controlling the lsi and communications between the controllers. when sio interrupts are enabled, an interrupt is generated as soon as execution of the sio completes, causing the program to jump to address 4. the p1-3 pin has multiplexed functions for a buzzer output pin. one of four frequencies within the range from 0.75 khz, 1 khz, 1.5 khz and 3 khz can be selected for buzzer output (when the 75-khz clock is used). the buzzer is driven at the selected frequency in one of four modes: continuous, single-shot, 10-hz intermittent, and 10-hz intermittent at 1-hz intervals. the p7-2 pin has multiplexed functions for an external interrupt input pin. when interrupts are enabled and a pulse of 1.65 s to 4.96 s or more (13.3 s to 40 s when the 75-khz clock is used) is applied to this pin, an interrupt is generated and the program jumps to address 1. the input logic and rising/falling edge can be selected for interrupt inputs. this input can be applied as the clock gate signal to the internal 8-bit timer/counter, which allows input pulse width to be detected and measured. (note) backup release is enabled or disabled in port units. (note) upon a system reset, the pins are set to i/o port input. (note) when the 32.768-khz crystal oscillator or the cr oscillator is used, the general-purpose counter is used as a timer. mv dd i nput instruction release enable mv ss r fin ctin mv dd mv ss (when p1-0 is used for general-purpose counter) mv dd mv dd i nput instruction release enable mv ss (when used for i/o port)
TC94A58FAG 2005-12-7 10 pin no. symbol pin name function and operation remarks 8 mv dd 9 mv ss power supply pins for controller block power supply pins for the controller block. normally, v dd = 3.0 to 3.6 v. when only the cpu operates (when the 75-khz/32.768-khz oscillator is used), it can operate at v dd = 1.8 to 3.6 v. in the backup state (when the ckstp instruction is executed), current dissipation decreases (10 a or below), allowing the power supply voltage to be reduced to 1.0 v. raising the voltage on mvdd pin from 0 v to 1.8 v or higher triggers a system reset, causing the program to start from address 0 (power-on reset). (note) at power-on reset operation, allow 1 ms to 50 ms while the device power supply voltage rises. (note) the backup current is the total of currents for cv dd , mv dd and dv dd . 17 pdo output pin for a phase error signal between the efm and plck signals. drives one of four values: av dd , hi-z, v ref , av ss 18 tmax tmax detection result output pin. longer than specified cycle: drives a high level (av dd ) shorter than specified cycle: drives a low level (av ss ) within specified cycle: hi-z 19 lpfn inverted input pin for pll low-pass filter amplifier. 20 lpfo output pin for pll low-pass filter amplifier. 21 vcof vco filter pin 22 av ss cd processor control input/output pin ground pin for analog block ? mv dd mv ss av dd av ss vco v ref av dd lpfn lpfo v ref vcof av dd v ref r out4 av ss
TC94A58FAG 2005-12-7 11 pin no. symbol pin name function and operation remarks 23 slco dac output pin for generating data slice level. 24 rfi rf signal input pin. the value of zin1 can be selected using a cd command. 25 av dd power supply pin for analog block. normally, v dd = 3.0 to 3.6 v. in cd standby mode, turn this power supply off. ? 26 v ref analog reference voltage pin. normally, a voltage of 1/2 av dd is supplied (when v dd = 3.3 v, v ref = 1.65 v). ? 27 rfzi rfrp zero-cross signal input pin 28 rfrp rf ripple signal input pin 29 fei focus error signal input pin 30 sbad sunbeam addition signal input pin 31 tei tracking error input pin. the pin is read when tracking servo is turned on. 32 tezi tracking error/zero-cross signal input pin 33 foo focus equalizer output pin 34 tro cd processor control input/output pin tracking equalizer output pin av dd rfrp fei sbad tei v ref z in1 dac av dd rfi slco av dd tezi 1 k ? typ. 32 k ? typ. v ref z in2 av dd a v dd to a v ss r out3 av dd rfzi 1 k ? typ. 32 k ? typ. v ref z in2
TC94A58FAG 2005-12-7 12 pin no. symbol pin name function and operation remarks 35 rfgc control signal output pin for adjusting rf amplitude. drives three-level pwm signal (pwm carrier = 88.2 khz). 36 tebc tracking balance control signal output pin. drives three-level pwm signal (pwm carrier = 88.2 khz). 37 sel apc circuit on/off signal output pin. when laser is turned on, this pin will be in a high-impedance state. 38 fmo feed equalizer output pin. drives three-level pwm signal (pwm carrier = 88.2 khz). 39 dmo cd processor control input/output pin disc equalizer output pin. drives three-level pwm signal (pwm carrier = 88.2 khz). 40 cv dd 43 cv ss power supply pins logic power supply pins for the cd processor block and 16.9344-mhz dedicated crystal oscillator. normally, the same power supply as that for the mv dd and mv ss pins is connected. in cd standby mode, current dissipation decreases. 41 xo 42 xi crystal oscillator pins input/output pins for the cd processor-dedicated crystal oscillator. connect a 16.9344-mhz crystal oscillator. this clock is used as the cd processor system clock and controller system clock. upon a system reset, this clock is supplied as the controller system clock and starts the cpu. the crystal oscillator can be stopped by program. if the 75/32.768-khz or external cpu clock is selected as the controller system clock, the cd processor oscillator is stop ped by program when the cd processor is turned off. (note) when switching the controller system clock from the controller oscillator to the cd crystal oscillator, make sure that the cd crystal oscillator is sufficiently stable. av dd cv dd cv ss xo r out1 r fxt1 xi cv dd cv ss av dd v ref r out3 av dd v ref r out3
TC94A58FAG 2005-12-7 13 pin no. symbol pin name function and operation remarks 44 dv dd da converter block power supply pin the TC94A58FAG consumes less current in cd standby mode. 45 ro r-channel data forward rotation output pin 46 dv ss da converter block ground pin 47 lo l-channel data forward rotation output pin 48 dvr audio dac output reference voltage pin dv dd v ss dv ss dv dd ro/lo dv r
TC94A58FAG 2005-12-7 14 maximum ratings (ta = 25c, cv dd = dv dd = av dd = mv dd ) characteristics symbol rating unit supply voltage v dd ? 0.3 to 4.0 v cv dd pin v in1 ? 0.3 to cv dd + 0.3 av dd pin v in2 ? 0.3 to av dd + 0.3 dv dd pin v in3 ? 0.3 to dv dd + 0.3 mv dd pin v in4 ? 0.3 to mv dd + 0.3 input voltage (note 1) v in5 ? 0.3 to 6.0 v power dissipation p d 400 mw operating temperature t opr ? 40 to 85 c storage temperature t stg ? 65 to 150 c note 1: v in1 ; pins 41 and 42 v in2 ; pins 17 to 39 (excluding power supply pins) v in3 ; pins 45, 47 and 48 v in4 ; pins 1 to 13 and 49 to 64 (excluding power supply pins) v in5 ; pins 14, 15 and 16
TC94A58FAG 2005-12-7 15 electrical characteristics (ta = 25c, cv dd = mv dd = dv dd = av dd = 3.3 v, v ref = 1.65 v unless otherwise stated ) characteristics symbol test circuit test condition min typ. max unit v dd1 cpu and cd in operation mv dd = cv dd > = = av dd (note 4) 3.0 ~ 3.6 v dd2 cpu in operation (cd standby, 16.9344-mhz crystal oscillator/cr oscillator used) (note 4) 3.0 ~ 3.6 operating supply voltage range v dd3 ? only cpu in operation (cd standby, 75-khz/32.768-khz crystal oscillator used) (note 5) 1.8 ~ 3.6 v memory hold voltage range mv hd ? crystal oscillator stopped (ckstp instruction executed) (note 4) 1.0 ~ 3.6 v i dd1 cpu and cd in operation (xi = 16.9344-mhz crystal oscillator used) ? 30 50 i dd2 only cpu in operation (xi = 16.9344-mhz crystal oscillator used) ? 1.5 ? ma i dd3 cpu in operation (mxi = 75-khz crystal oscillator connected) ? 50 100 a operating power supply current (note 2) i dd4 ? standby mode (only crystal oscillator in operation, mxi = 75 khz) ? 30 80 a memory hold current mi hd ? (cv dd /mv dd /av dd /dv dd ) crystal oscillator st opped (ckstp instruction executed) ? 0.1 10 a f mxt (mxi-mxo) crystal oscillator selected (note 3) (note 5) 30 ~ 100 khz oscillation fr equency f xt ? (xi-xo) (note 4) ? 16.9344 ? mhz crystal oscillator start time t st ? (mxi-mxo) crystal oscillator f mxt = 75 khz/32.768 khz ? ? 1.0 s r fxt1 (xi-xo) 0.5 1.0 2.0 crystal oscillator amplifier feedback resistance r fxt2 ? (mxi-mxo) ? 20 ? m ? r out1 (xo) 0.25 0.5 1.0 crystal oscillator output resistance r out2 ? (mxo) 50 100 200 k ? dropout voltage detect voltage v det ? 1.4 1.5 1.6 v dropout voltage detector operating current i dd -v d ? (mv dd ) dropout voltage detector enabled ? 100 ? a note 2: the operating power supply current includes the total current through all cv dd , mv dd , dv dd and av dd power supply pins. note 3: design and specify constants according to the crystal oscillator to be connected. note 4: the values are guaranteed when cv dd = mv dd = dv dd = av dd = 3.0 to 3.6 v, ta = ? 40 to 85c. note 5: the values are guaranteed when cv dd = mv dd = dv dd = av dd = 1.8 to 3.6 v, ta = ? 30 to 75c. general-purpose counter (ctin) characteristics symbol test circuit test condition min typ. max unit frequency range f ct ? v in = 0.2 v p-p (note 6) 0.1 ? 20 mhz input amplitude range v ct ? (note 6) 0.2 ? 2.0 v p-p operating power supply current i dd-ct ? general-purpose counter operating current, f in = 20 mhz ? 0.5 ? ma input amplifier feedback resistance r fin ? (ctin) 200 350 1000 k ? note 6: the values are guaranteed when cv dd = mv dd = dv dd = av dd = 3.0 to 3.6 v, ta = ? 40 to 85c.
TC94A58FAG 2005-12-7 16 lcd common and segment outputs (com1 to com4, s1 to s16) characteristics symbol test circuit test condition min typ. max unit high level i oh1 v oh = 2.9 v (lcd output) ? ? 300 ? output current low level i ol1 ? v ol = 0.4 v (lcd output) ? 450 ? a 1/2 level v bs2 no load (common output, 1/2 bias method) 2.3 2.5 2.7 1/3 level v bs1 1.47 1.67 1.87 bias current 2/3 level v bs3 ? no load (lcd output, 1/3 bias method) 3.13 3.33 3.53 v lcd operating power supply current i dd- lcd ? lcd driver operating current ? 50 ? a i/o ports (p1-0 to p6-3, p8-0, p8-1, p7-0 to p7-3) characteristics symbol test circuit test condition min typ. max unit i oh2 v oh = 2.9 v (p1-0 to p1-3, p6-2, p6-3, p8-0, p8-1) ? 1.0 ? 2.0 ? high level i oh3 v oh = 2.9 v (p2-0 to p5-3, p6-0, p6-1) ? 3.0 ? 6.0 i ol2 v ol = 0.4 v (p1-0 to p1-3 , p6-2 , p6-3, p8-0, p8-1) 1.0 2.0 ? i ol3 v ol = 0.4 v (p7-0 to p7-3) 5 15 ? i ol4 v ol = 0.4 v (p2-2, p2-3, p3-0 to p5-3, p6-0, p6-1) 3.0 6.0 ? output current low level i ol5 ? v ol = 0.4 v (p2-0, p2-1) 15 30 ? ma v ih = 3.3 v, v il = 0 v (p1-0 to p6-3, p8-0, p8-1) ? ? 1.0 input leakage current i li ? v ih = 5.5 v, v il = 0 v (p7-0 to p7-3) ? ? 1.0 a high level v ih ? v dd 0.8 ~ mv dd input voltage low level v il ? ? 0 ~ mv dd 0.2 v r in1 (p6-0 to p6-3, p8-0, p8-1) pull-down/up specified 25 50 120 input pull-up/down resistance r in2 ? (p3-0) test input pulled down ? 10 ? k ? ad converter (adin1 to adin4) characteristics symbol test circuit test condition min typ. max unit analog input voltage range v ad ? adin1 to adin4 0 ~ mv dd v resolution v res ? ? ? 6 ? bit mv dd = 1.8~3.6v, ta = ? 30~75c (note 7) ? ? 2.0 total conversion error ? ? mv dd = 2.0~3.6v, ta = ? 40~85c (note 7) ? ? 1.0 lsb analog input leakage current i li ? v ih = 3.3 v, v il = 0 v (adin1 to adin4) ? ? 1.0 a note 7: the values are guaranteed when cv dd = dv dd = av dd = 3.0 to 3.6 v.
TC94A58FAG 2005-12-7 17 pdo, tmax, rfgc, tebc, fmo, dmo, tro, foo, and sel output characteristics symbol test circuit test condition min typ. max unit high level i oh6 v oh = 2.9 v (sel, tmax) ? 2.0 ? ? output current low level i ol4 ? v ol = 0.4 v (sel, tmax) 2.0 ? ? ma r out3 (rfgc, tebc, fmo, dmo, tro, foo) ? 3.0 ? output resistance r out4 ? (pdo) ? 5.0 ? k ? v ref output on resistance r on ? (rfgc, tebc, fmo, dmo, pdo) ? ? 500 ?
TC94A58FAG 2005-12-7 18 transfer delay time (bck, lrck, aout, dout, ipf, sbok, clck, data, sfsy, sbsy) characteristics symbol test circuit test condition min typ. max unit high level t plh ? ? 10 ? transfer delay time low level t phl ? ? ? 10 ? ns cd processor ad conversion block (fei, tei, rfrp, sbad) characteristics symbol test circuit test condition min typ. max unit resolution ? ? (fei, tei, rfrp, sbad) ? 8 ? bit (fei, tei, rfrp) ? 176.4 ? sampling frequency ? ? (sbad) ? 88.2 ? khz conversion input range ? ? av dd = 3.3 v (fei, tei, rfrp, sbad) 0.15 av dd ? 0.85 av dd v cd processor da conversion block ( focus tracking system ) characteristics symbol test circuit test condition min typ. max unit number of bits ? ? (foo, tro) ? 5 ? bit sampling frequency ? ? (foo, tro) ? 2.8 ? mhz conversion output range ? ? av dd = 3.3 v (foo, tro) av ss ? av dd v cd processor pll/vco block characteristics symbol test circuit test condition min typ. max unit input/output signal range ? ? (lpfn, lpfo) av ss ? av dd v frequency characteristic ? ? (lpfn-lpfo) ? 3db point (gain = 1) ? 8 ? mhz oscillation center frequency ? ? lpfo = v ref ? 34 ? mhz [vcogsl] bit = low ? 30 ? + 30 frequency variable range ? ? [vcogsl] bit = high ? 40 ? + 40 % cd processor comparator (tezi, rfzi) characteristics symbol test circuit test condition min typ. max unit input range ? ? (tezi, rfzi) av ss ? av dd v hysteresis voltage ? ? (tezi, rfzi) v ref reference ? 50 ? + 50 mv input resistance z in2 ? (tezi, rfzi) ? 10 ? k ? cd processor data slicer (rfi/slco) characteristics symbol test circuit test condition min typ. max unit input amplitude ? ? (rfi) v ref reference 0.6 1.2 2.0 v p-p ? 20 ? input resistance z in1 ? (rfi) set resistance by cd command ? 10 ? k ? dac resolution ? ? (slco) r-2r dac ? 6 ? bit dac output conversion range ? ? (slco) r-2r dac 0.75 v ref ? 1.25 v ref v dac output impedance ? ? (slco) r-2r dac ? 2.5 ? k ?
TC94A58FAG 2005-12-7 19 1-bit da converter characteristics symbol test circuit test condition min typ. max unit total harmony distortion thd + n ? 1-khz sine wave, full-scale input ? ? 85 ? 77 db s/n (1) internal zero detect = off 85 91 ? s/n ratio s/n (2) ? internal zero detect = on 95 100 ? db dynamic range dr ? 1-khz sine wave, input reduction of ? 60db 83 90 ? db crosstalk ct ? 1-khz sine wave, full-scale input ? ? 90 ? 83 db analog output level dacout ? 1-khz sine wave, full-scale input 790 825 860 mvrms
TC94A58FAG 2005-12-7 20 package dimensions weight: 0.32 g (typ.)
TC94A58FAG 2005-12-7 21

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